Etching-free pixel definition in InGaN green micro-LEDs

The traditional plasma etching process for defining micro-LED pixels could lead to significant sidewall damage. Defects near sidewall regions act as non-radiative recombination centers and paths for current leakage, significantly deteriorating device performance. In this study, we demonstrated a novel selective thermal oxidation (STO) method that allowed pixel definition without undergoing plasma damage and subsequent dielectric passivation. Thermal annealing in ambient air oxidized and reshaped the LED structure, such as p-layers and InGaN/GaN multiple quantum wells. Simultaneously, the pixel areas beneath the pre-deposited SiO2 layer were selectively and effectively protected. It was demonstrated that prolonged thermal annealing time enhanced the insulating properties of the oxide, significantly reducing LED leakage current. Furthermore, applying a thicker SiO2 protective layer minimized device resistance and boosted device efficiency effectively. Utilizing the STO method, InGaN green micro-LED arrays with 50-, 30-, and 10-µm pixel sizes were manufactured and characterized. The results indicated that after 4 h of air annealing and with a 3.5-μm SiO2 protective layer, the 10-µm pixel array exhibited leakage currents density 1.2 × 10−6 A/cm2 at −10 V voltage and a peak on-wafer external quantum efficiency of ~6.48%. This work suggests that the STO method could become an effective approach for future micro-LED manufacturing to mitigate adverse LED efficiency size effects due to the plasma etching and improve device efficiency. Micro-LEDs fabricated through the STO method can be applied to micro-displays, visible light communication, and optical interconnect-based memories. Almost planar pixel geometry will provide more possibilities for the monolithic integration of driving circuits with micro-LEDs. Moreover, the STO method is not limited to micro-LED fabrication and can be extended to design other III-nitride devices, such as photodetectors, laser diodes, high-electron-mobility transistors, and Schottky barrier diodes.

In Fig. S2a to Fig. S2c, we presented optical and SEM images (by Helios system) of pixels before annealing, after annealing, and after removing SiO 2 using HF vapor.The n-electrode regions were not etched in this illustration.No peeling off of SiO 2 was found in these good devices.Section SM2: In the STO method proposed in this work for fabricating micro-LEDs, the removal of the SiO 2 mask must be highly selective to the oxide layer to avoid the risk of leakage or even short circuits.To demonstrate the good selectivity of HF vapor between them, we conducted the measurement of the height difference before and after the removal of SiO 2 using a DEKTAK XT-profile meter, as shown in Fig. S3a to Fig. S3c.In the test, the thickness of patterned SiO 2 was approximately t 1 =3530 nm.After thermal annealing, the height difference between the oxide layer plane and the SiO 2 plane was reduced to a range of approximately t 2 =3200 to 3350 nm.The height increase of the oxide plane during oxidation is attributed to thermal expansion and the formation of internal porous.After completely removing all SiO 2 using HF vapor, the oxide plane is still approximately 150 to 300 nm higher than the smooth wafer surface (t 3 ).The thickness of the oxide layer lost during the HF vapor etching process is given by t=t 1 −t 2 −t 3 .Due to the highly roughened surface after oxidation and the limited resolution of the profilometer, we cannot provide a precise etching rate of the oxide layer in HF vapor.However, it is evident that compared to the 3530 nm SiO 2 , the value of t is extremely small, providing strong evidence for the high selectivity of the SiO 2 removal process.In Fig. S4a and Fig. S4b, we present SEM images to show the changes in pixels before and after HF vapor etching.It can be observed that the oxide layer maintains a similar surface morphology to before etching.The oxide layer plane is slightly higher than the pixel plane, enveloping it, consistent with our profilometer measurements above.Some residual SiO 2 particles are still found within the pixel, indicating that additional etching time with HF vapor and ultrasonic cleaning may be necessary to completely remove them and minimize their impact on device resistance.The edges of the pixels after SiO 2 removal are quite rough, possibly related to the inherent roughness of the SiO 2 mask itself before annealing.In this work, we utilized a dry etching process for SiO 2 patterning.Equipment conditions fluctuating such as chamber environment and plasma source may lead the variation of sidewall morphology.Fig. S5a and Fig. S5b show SEM images of a reference sample.The etched SiO 2 sidewalls are smoother and steeper, resulting in smoother edges of the pixels after annealing and HF etching.However, we believe that these changes from process condition variations and do not significantly impact the methodology and conclusions of this work.Furthermore, the low leakage current in our device shown in the manuscript can indirectly demonstrate the etching selectivity of HF vapor to SiO 2 and the oxide layer.This is because once the oxide layer is significantly depleted, it will expose the pixel sidewalls, leading to leakage and non-radiative recombination.
If the oxide layer is etched further, it may directly result in a short circuit between the n and p electrodes.
Clearly, these issues did not occur in our experiments.
Section SM3: The cathodoluminescence (CL) images measured by the Zeiss Merlin system shown in Fig. S6a to Fig. S6d suggest the emission from pixels is generally uniform, and any observed non-uniformities may stem from epitaxial growth, the STO process, and other fabrication processes.The CL measurement condition: wavelength 560 nm, band pass 50 nm, voltage: 15 KV, current 500 pA.Section SM4: Under SiO 2 protection, the LED structure remained intact, exhibiting a clear superlattice structure in Fig. S7a and Fig. S7b.However, once the SiO 2 protection was lost, most of the p-layer and MQW were oxidized and show the distinctly polycrystalline nature of the material formed by oxidation, with multiple crystal orientations mixed together in Fig. S7c and Fig. S7d.

Section SM5:
We cut pixels (different from the one for TEM in the manuscript) using laser cutting and mechanical cracking along the patterned SiO 2 to observe their cross-sections by the Helios SEM system, which was after the STO process but without suffering from the HF vapor etching.The results in Fig. S8 show that, in some pixels, we observed crack propagation and lateral oxidation.This suggests that the cracking phenomenon in the main manuscript is not an isolated case.The crack may result from the thermal mismatch between the oxide and nitride materials during the heating and cooling stages of the STO process.Compared to the non-annealed reference sample, samples annealed for 4 and 8 hours still maintained a relatively smooth surface overall, consistent with the information in the previous SEM images.However, locally, we observed that the annealed samples exhibited numerous protrusions on the surface, and this phenomenon was slightly more pronounced in the sample annealed for 8 hours as shown in Fig. S9a and Fig. S9b.We believe this was due to oxygen diffusion from SiO 2 into the LED, resulting in surface slight oxidation of the surface and a minor increase in surface roughness.

Section SM10:
In this work, we employed SiO 2 as a mask to prevent oxidation and damage to micro-LED pixels during the thermal annealing process.However, oxygen diffusion exhibits isotropy, meaning oxygen atoms can also diffuse laterally beneath the SiO 2 protection.Therefore, we believe that the lateral diffusion rate of oxygen and its impact on the device play a crucial role in determining whether higher pixel density can be achieved.Based on this, we have supplemented a design strategy to achieve a higher resolution micro-LED array shown in Figs.S13 and S14.
In Fig. S13, "L" represents the layout line width, "S" is the layout space width, and "d" is the lateral oxidation length beneath the SiO 2 protection.Due to lateral oxidation, the actual pixel line width becomes   From the TEM image measured in this work, d is approximately 300 nm.This means that, under the described model, we can achieve micro-LED designs with minimum L'/S' = 600 nm/600 nm.
Indeed, achieving such small-dimension pixels involves complex factors, requiring precise control of experimental conditions such as annealing time and ambient conditions to control the crack formation and ensure uniformity and yield.

Section SM11:
In this work, we chose to fabricate arrays rather than individual micro-LEDs because arrays can better reflect the average performance of pixels such as leakage current density and efficiency.In fact, the exact same process can be applied to the fabrication of individual micro-LEDs, as depicted in Fig. S15.The only difference from array manufacturing is that each pixel has its own n-electrode and p-electrode, no longer shared among all pixels in the array.Unlike traditional etching processes, we did not selectively remove the active regions in our approach; instead, we oxidized them into oxides.However, this does not affect the subsequent mass transfer processes for micro-LED pixels.Flip-chip processes, wafer dicing, substrate removal, and pixel transfer can all continue to be applied to our micro-LEDs.Since the periphery of our pixels is entirely composed of highresistance oxides, processes such as wafer dicing, and pixel bonding to control circuits (electrodes) will not lead to short-circuit or pixel damage leakage.Based on our understanding, we believe that the micro-LED fabrication method we proposed, based on STO, is compatible with mainstream micro-LED mass transfer technologies.

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Fig. S1.(a) Optical microscopy and (b) SEM images of peeling off of SiO2 after the STO process.

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Fig. S2.Optical microscopy and SEM images of pixels (a) before annealing, (b) after annealing, and (c) after SiO2 removal.

Fig. S4 .
Fig. S4.SEM images of the pixel (a) before and (b) after SiO2 removal after the STO.

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Fig. S5.SEM images of the pixel (a) before SiO2 removal and (b) after SiO2 removal after STO (reference sample).

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Fig. S6.(a), (c) SEM and (b), (d) CL images of pixels after SiO2 removal by the HF vapor.

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Fig. S7.(a) Magnified TEM image of the LED MQW structure under SiO2 protection, (b) Fast Fourier Transform (FFT) images of MQW, (c) magnified TEM image of the oxidized material without SiO2 protection, (d) FFT image of oxide formed by the thermal annealing.

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Fig. S8.Cross-section SEM images of the pixel protected by SiO2 after the STO process (with cracking)

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Fig. S10.EL spectrums for all samples mentioned in the manuscript.

Fig. S12 .
Fig. S12.Fabrication process and corresponding SEM images of STO for 2.3-µm micro-LED array fabrication.The inset image is the EL emission of 2.3-µm micro-LED pixels.

L
' = L − 2d, and the actual space width becomes S' = S + 2d.According to this definition, the actual pixel size L' can be reduced to any dimension until L ≤ 2d (L' ≥ 0).In a special design, If the same line and space width is desired (i.e., L' = S'), then L − 2d = S + 2d, and L = 4d + S. When S = 0, L reaches its minimum value of 4d, and L' = S' = L − 2d = 2d.This situation is shown in Fig.S14.

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Fig.S13.A design strategy to achieve a higher resolution micro-LED array.

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Fig. S14.A design strategy to achieve a limitation size when L'=S'.

Fig. S15 .
Fig. S15.Individual mesa fabrication and its mass transfer for display applications.